Electrically erasable programmable read only memories (EEPROM) have gained widespread acceptance in the industry. EEPROM cells do not require the periodic refresh pulses needed by the capacitive storage elements of conventional one-device dynamic random access memory (DRAM) cells. This presents an appreciable power savings. Because they rely upon charge injection/removal to establish the stored logic state, the write cycles of EEPROM cells are appreciably longer than those of DRAM's.
Several exemplary EEPROM technologies will now be discussed.
U.S. Pat. No. 3,500,142 (issued Mar. 10, 1972, to Kahng and assigned to AT&T) describes a programmable field effect transistor (FET) wherein the gate electrode is defined by a layer of silicon oxide disposed over a portion of the silicon substrate between two P-type diffusion regions, a layer of zirconium on the oxide layer, a layer of zirconium oxide on the zirconium layer, and a control electrode on the zirconium oxide layer. The zirconium layer serves as a "floating gate" structure. That is, the zirconium layer is not directly coupled to a source of applied potential. Rather, it is allowed to assume its own voltage state (i.e., "float") as a function of the capacitive coupling between it and the overlying control electrode. To program the cell, a high bias is applied to the control electrode. The capacitive coupling between the control electrode and the floating gate is such that a channel region is induced in the underlying portion of the silicon substrate between the two P-type diffusion regions. At this high bias potential, some carriers will have sufficient energy to be injected through the silicon oxide layer into the floating gate. This injection of carriers (by avalanche breakdown or by hot electron effects) will provide an amount of charge to the floating gate that is determined by the applied bias. To erase the cell, a negative bias is supplied to the control electrode such that the charge carriers previously accumulated in the floating gate are injected through the oxide layer into the silicon substrate.
In other EEPROM cells, a non-conductive charge trapping layer is used in place of the above zirconium floating gate. In U.S. Pat. No. 3,878,549 (issued Apr. 15, 1975, to Yamazaki et al) the FET gate electrode is comprised of a layer of silicon oxide contacting the silicon substrate, a thin layer of silicon nitride over the silicon oxide, a plurality of silicon clusters disposed on the nitride layer, a second layer of silicon nitride overlying the silicon clusters, and a control electrode. At high applied bias, electrons will be injected through the silicon oxide layer and the first silicon nitride layer, where they will be trapped by the silicon clusters overlying the silicon nitride layer. In Japanese Published Patent Application No. J55-87490-A (filed Dec. 25, 1978 by Endou and assigned to Toshiba), a plurality of interposed silicon oxide and silicon nitride layers are provided. Charge injected from the substrate is trapped by one or more of the silicon nitride films depending on the magnitude of the applied bias. PCT Application No. 80-01179 (filed Sept. 13, 1979, by Trudel et al and assigned to NCR) discloses a non-volatile memory cell in which charge injected from the silicon substrate passes through a silicon oxide layer where it is trapped by a layer of silicon nitride. U.S. Pat. No. 3,649,884 (issued Mar. 14, 1972, to Haneta and assigned to NEC) discloses a field effect transistor with a gate assembly that includes an intervening layer of silicon rich silicon oxide that traps charge injected from the silicon substrate through an intervening layer of stoichiometric silicon oxide.
In the references discussed above, the memory cell is programmed by charge injection from the induced channel region of the substrate, through an intervening insulating layer, into a conductive or non-conductive charge trapping layer. In practice, it is difficult to precisely control the extent of charge injection from the induced channel region. The silicon oxide layer separating the channel region from the overlying charge trapping layer must be thin enough to allow charge transfer and yet thick enough to allow the charge trapping layer to retain the stored charge. These characteristics are very sensitive to changes in the thickness and/or stoichiometry of the oxide film.
In order to surmount these difficulties, researchers have attempted to construct EEPROM cells that do not rely upon charge injection from an induced channel region. In U.S. Pat. No. 4,104,675 (issued Aug. 5, 1978, to DiMaria et al and assigned to the assignee of the present invention), the silicon substrate is covered with a thick layer of thermal silicon oxide and thin layers of pyrolytic silicon oxide. A layer of aluminum is disposed above the pyrolytic SiO.sub.2 layers. As shown in FIG. 7 of the patent, the aluminum layer serves as the gate electrode of an FET storage device with the pyrolytic SiO.sub.2 layers and the thermal SiO.sub.2 layer serving as the gate dielectric. The pyrolytic SiO.sub.2 layers have excess silicon incorporated in them. The amount of excess silicon is increased as a function of distance from the thermal SiO.sub.2 -silicon substrate interface. This increase in silicon concentration produces a graded band gap structure that is conducive to injection of holes and electrons from the aluminum electrode to the SiO.sub.2 -substrate interface. Thus, rather than relying on surface tunneling, the DiMaria patent shows a structure in which charge injection/removal takes place between a trapping center and an overlying charge injection structure. In practice, it would be difficult to construct a memory cell based upon the teachings of this patent, in that the thick silicon oxide layer is a poor trapping layer. That is, not enough charge would be trapped, and the charge which is trapped would be non-uniformily dispersed within the silicon oxide layer. As such, the effect of a given quantity of the trapped charge upon the threshold of EEPROM cell the device will vary from device to device.
Some of the above-noted shortcomings were recognized by DiMaria in his later work. See for example an article by DiMaria et al, entitled "Electrically-Alterable Read-Only-Memory Using Silicon-Rich SiO.sub.2 Injectors and a Floating Polycrystaline Silicon Storage Layer," Journal of Applied Physics, Vol. 52, No. 7, July 1981, pp. 4825-4842. As shown in FIG. 2 of this paper, a stoichiometric silicon oxide layer is sandwiched between two silicon-rich silicon oxide layers. The lower silicon-rich silicon oxide layer is disposed on a first polysilicon electrode, and the upper silicon-rich silicon oxide layer is disposed below a second polysilicon electrode. Charge transfer is effected between the two polysilicon electrodes through the two silicon-rich silicon oxide layers. The dual silicon-rich silicon oxide layers, in conjunction with the central stoichiometric silicon oxide layer, is commonly referred to as a dual electron injector structure (or DEIS). Note first that the lower polysilicon electrode serves as a floating gate that stores injected charge. Such a structure will store more charge than the thick oxide layer of the above-described patent, while storing the injected charge in a more uniform manner. Moreover, as opposed to the patent, the amount of silicon in the lower and upper silicon rich silicon oxide layers is relatively similar, and the intervening silicon oxide layer does not have any excess silicon.
However, the above-described memory cell suffers from still another problem. In order to provide a reliable charge storage structure, a conductive layer is used. Thus, similarly to the Kahng '142 patent previously cited, reliance is placed upon the capacitive coupling between the floating gate and the control gate to program and/or erase the cell. This situation is incompatible with current device technologies which rely on lower applied voltages. Moreover, because it is difficult to precisely control the characteristics of the oxide layer between the two polysilicon layers, the capacitive characteristics must be compensated by increasing the size of the lower polysilicon electrode relatively to the upper polysilicon electrode. This is also incompatible with current device scaling trends.
Accordingly, there is a need in the art for an EEPROM storage cell that incorporates a nonconducting charge trapping structure that is not programmed by hot carrier injection and which is compatible with current device scaling trends.